The invention relates to a method and an apparatus for video decoding and de-interlacing, and more particularly, to a method and an apparatus for video decoding and de-interlacing utilizing a shared storage device.
MPEG2 is a standard that has been proposed for the digital encoding of video signals. MPEG2 allows for signals to be encoded on either an interlaced or progressive basis.
The term interlaced is used to refer to image data that is represented using, e.g., two alternating image fields. One field of an interlaced video frame normally corresponds to the odd lines of pixels in the frame with the other field corresponding to the even lines of the frame. During display, the lines of one field are scanned, e.g., output to a display device. The lines of the second field are then scanned, so that they are interlaced on the display device with the lines of the first field. In this manner, when interlaced images are displayed, odd and even lines of image data are updated on an alternating basis.
In the case of progressive display, image data is displayed sequentially, e.g., starting at the top left corner of an image proceeding to the bottom right corner. Thus, in the progressive display case, the lines of an image are displayed or updated on a sequential basis without lines being skipped.
In a series of progressive video display, the positioning of the horizontal display lines is consistent from image to image. Accordingly, each newly displayed progressive image normally will completely replace the previous image on a display assuming that the images are the same size. In the case of interlaced video display, each frame includes two fields which correspond to spatially different, e.g., horizontal odd and even lines, of a display device. Accordingly, in the case of interlaced images, each field updates only a portion of the displayed image. Because fields of an interlaced image normally correspond to images at different times, merely combining fields 1 and 2 of an interlaced frame can cause blurring and other image distortions when motion is present. For this reason, conversion of interlaced images to progressive images normally involves some form of motion detection and the application of processing which is a function of detected motion.
Presently video images are usually encoded to be displayed as interlaced video. Unfortunately, most recent display devices such as monitors for computers and projectors are designed to display progressive display images.
The ability to efficiently convert between interlaced and progressive image formats continues to increase in importance due, in part, to the ever increasing use of computers. Notably, when television scenes or other data represented as interlaced images are to be displayed on a progressive display, they normally first have to be converted into progressive image data.
High speed memory is normally used in video processing applications which convert between image formats. This is so that real time, or near real time, processing of video data can be achieved. While the cost of memory has dropped considerably in recent years, memory still remains a significant cost component of many image and video processing systems. This is because a relatively large amount of memory is normally required for video applications. In consumer applications and other applications where cost is a concern, it is desirable to minimize the amount of memory required to implement an image processing system or device.
Please refer to FIG. 1. FIG. 1 shows a block diagram of a video display system 100 according to the prior art. The video display system 100 comprises an MPEG2 decoder 110 receiving MPEG2 coded video data streams from a video source (not shown), for decoding the video data to generate decoded video data. In order to execute the decoding function with the decoder 110 smoothly and efficiently, a first memory is coupled to the decoder 110 for video frame buffering. The video display system 100 then comprises an interlaced display unit 125 coupled to the first memory 120. The interlaced display unit 125 is capable of processing decoded image data stored in the first memory 120 for further displaying on an interlaced display (not shown). The video display system 100 also comprises an interlaced/progressive converter 130 coupled to the interlaced display unit 125 for de-interlacing interlaced image data from the interlaced display unit 125 to generate corresponding progressive video data and outputting the converted video data to a progressive display (not shown) for further displaying. Again, in order to execute the de-interlacing function with the converter 130, a second memory 140 is also coupled to the converter 130 for video frame buffering.
For the prior art decoder 110 to perform the decoding function towards different types of video frames, such as I picture frames, P picture frames (together called reference picture frames), and B picture frames, the first memory 120 usually contains storage space for buffering at least three video frames (i.e., six fields). For the interlaced/progressive converter 130 to perform motion detection and as a result switch between intra-field and inter-field interpolation, the second memory 140 then requires storage space for buffering two video frames (i.e., four fields). As a whole, to properly execute designed functions of the prior art video display system 100, the system 100 requires a storage capacity of at least five video frames.
The prior art interlaced/progressive converter 130 usually can perform motion-adaptive de-interlacing operations with video information incorporating not more than four video fields due to the limited storage space of the second memory 140. That is, for each presently displaying frame, switching between intra-field and inter-field interpolation is based on video information of at most four video fields. It is not applicable for the prior art video display system 100 to perform motion-adaptive de-interlacing operations based on an even larger number of fields in order to acquire a more precisely predicted display result.
As can be seen in FIG. 1, operations of the prior art video display system 100 involve data exchange between the first memory 120 and the decoder 110, between the first memory 120 and the interlaced display unit 125, and also between the second memory 140 and the interlaced/progressive converter 130. Therefore a total memory bandwidth requirement of the prior art video display system 100 is considerably large. This is conventionally not desirable for video display system design.
In order to reduce the cost as well as memory bandwidth requirement of video systems that perform decoding and conversion operations, there is a need for methods and an apparatus which allow for a reduction in the amount of memory required to implement such systems. In addition, in order to perform more well-referenced motion-adaptive de-interlacing operations, methods and an apparatus capable of such functionality is also desired. It is desirable that any new methods and apparatus be suitable for implementation in computer systems as well as televisions sets, set top boxes, and other video applications.